A strategy aimed at decreasing dielectric loss in coplanar waveguides (CPWs) and qubits involves the creation of trenches in the underlying substrate within the gaps of the overlying metallization. Participation of contamination layers residing on surfaces and interfaces in these designs can be reduced due to the change in the effective dielectric properties between the groundplane and the conductor metallization. Although finite element method approaches have been previously applied to quantify this decrease, an analytical method is presented that can uniquely address geometries possessing small to intermediate substrate trench depths. Conformal mapping techniques produce transformed CPW and qubit geometries without substrate trenching but a nonuniform contamination layer thickness. By parametrizing this variation, one can calculate surface participation through use of a 2-D, analytical approximation that properly captures singularities in the electric field intensity near the metallization corners and edges. Examples demonstrate two regimes with respect to substrate trench depth that capture an initial increase in substrate-to-air surface participation due to the trench sidewalls and an overall decrease in surface participation due to the reduction in the effective dielectric constant and are compared with experimental measurements to extract loss tangents on this surface.