About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
CF 2016
Conference paper
An architecture for near-data processing systems
Abstract
Near-data processing is a promising paradigm to address the bandwidth, latency, and energy limitations in today's com-puter systems. In this work, we introduce an architecture that enhances a contemporary multi-core CPU with new features for supporting a seamless integration of near-data processing capabilities. Crucial aspects such as coherency, data placement, communication, address translation, and the programming model are discussed. The essential compo-nents, as well as a system simulator, are realized in hardware and software. Results for the important Graph500 bench-mark show a 1.5x speedup when using the proposed archi-Tecture.