An architecture for boundary-based segmentation

Abstract

A novel hardware architecture for extracting region boundaries in two raster scan passes through a binary image is presented. The first pass gathers statistics regarding the size of each object contour. This information is used to dynamically allocate available memory for storage of boundary codes. In the second raster pass, the same architecture constructs lists of Grid-Joint Codes to represent the perimeter pixels of each object. These codes, referred to variously as "crack" codes or "raster-chain" codes in the literature, are later decoded by the hardware to reproduce the ordered sequence of coordinates surrounding each object. This list of coordinates is useful for the variety of shape recognition and manipulation algorithms which utilize boundary information. We present results of software simulations of the VLSI architecture, along with measurements of the coding efficiency of the basic algorithm, and estimates of the overall chip complexity. © 1988 SPIE.