An all digital frequency-locked loop immune to hysteresis effects for power management of multicore processors

Abstract

Low power design has always been critical to high performance. With the latest technologies, being able to significantly reduce any portion of the overall system power becomes an absolute requirement for extending the lifetime of the system. Clock generation and clock tree distribution are always identified as a significant portion of the power dissipated in a chip. We describe here a servocontrol circuit method that will provide both a lower power clock generation scheme as well as automated power management using the clock elements. The self correcting nature of the circuits proposed also offer good immunity against hysteresis effects. ©2010 IEEE.