Advanced chemical-mechanical planarization (CMP) for enabling silicon carrier integration with through-vias and fine pitch wiring

Abstract

Three novel chemical-mechanical planarization (CMP) processes were developed to facilitate fabrication of a silicon carrier that incorporates through-vias and fine-pitch wiring. The first CMP process was tailored towards the planarization of Cu-lined deep silicon through-vias, the second dealt with the polishing of a polyimide cap seal at the top of the vias, and the third allowed for integration of wiring levels with large open area pads. Electrical isolation and surface planarization of partially copperplated deep vias was achieved by keeping wafers wet throughout the entire Cu polish, liner polish, brush clean and post-CMP cleaning steps which included a megasonics clean resulting in CMP residue-free deep vias. These deep vias were filled with a conductive Cu composite paste. After paste sintering, the porous Cu composite fill was hermetically sealed using a novel polyimide (PI) via seal process. In order to planarize the wafer surface after PI cure, a CMP process was developed to remove the excess PI, creating a sealed PI cap at the top of the through-vias. This permitted further integration of wiring levels above the via. CMP of metals planes with over 85% open area was accomplished to keep topography below 100 nm.