Access transistor design and optimization for 65/45nm high performance SOI eDRAM

Abstract

A 65mn prototype embedded DRAM macro on partially depleted SOI (PD-SOI) substrate capable of <2.0ns latency and the enabling cell technology have been described previously [1,2]. In this paper, we focus on the cell design and optimization for best retention and performance which have been extended to the 45nm node. © 2008 IEEE.