A simulation design for verification and development of Fibre Channel

Abstract

The design of a simulator that is being used to verify Fibre Channel (a proposed standard for a serial I/O channel) is discussed. The complexity and incomplete state of the standard make verification through simulation both important and difficult. The simulator is also intended for subsequent use as a tool for Fibre Channel development. The need to meet the requirements of both verification and development has important implications of the simulator's design. These implications are described, together with some of the resulting tradeoffs.