Xiaoxiong Gu, Duixian Liu, et al.
ECTC 2014
A 0.13-μm SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P 1dB of 10 to 12 dBm, P sat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated. © 2006 IEEE.
Xiaoxiong Gu, Duixian Liu, et al.
ECTC 2014
Duckhyun Chang, Jerry G. Fossum, et al.
IEEE Electron Device Letters
Scott K. Reynolds, Arun S. Natarajan, et al.
RFIC 2010
Scott K. Reynolds, Brian A. Floyd, et al.
IEEE Journal of Solid-State Circuits