Publication
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Paper

A Ranking Algorithm for MOS Circuit Layouts

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Abstract

In the synthesis of digital circuits, one encounters the problem of identifying blocks which have been designed, so that there is no replication in the expensive effort of generating the physical layout of these blocks. We present a model for the synthesis of combinational logic into complex MOS circuits and present a ranking and unranking procedure to characterize the layout of each complex MOS circuit. © 1987 IEEE

Date

01 Jan 1987

Publication

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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