Matthew Arnold, David Piorkowski, et al.
IBM J. Res. Dev
In the synthesis of digital circuits, one encounters the problem of identifying blocks which have been designed, so that there is no replication in the expensive effort of generating the physical layout of these blocks. We present a model for the synthesis of combinational logic into complex MOS circuits and present a ranking and unranking procedure to characterize the layout of each complex MOS circuit. © 1987 IEEE
Matthew Arnold, David Piorkowski, et al.
IBM J. Res. Dev
Ravi Nair
Proceedings of the IEEE
H.W. Cain, M.H. Lipasti, et al.
PACT 2003
Ravi Nair, Samuel F. Antao, et al.
IBM J. Res. Dev