Publication
IEEE TC
Paper

A Novel Technique for Efficient Parallel Implementation of a Classical Logic/ Fault Simulation Problem

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Abstract

Existing methods in logic/fault simulation of VLSI array logic treat the problem as a nonnumeric one in which the basic primitives involved are Boolean operations, string matching/manipulation operations, etc. This paper describes a novel technique for reformulating the problem in terms of standard vector and matrix operation primitives which are well-supported on all scientific supercomputers, high-end mainframes, and minisupercomputers which provide vector/parallel hardware and software. The overall computing environment is assumed to be a scientific/engineering one, with Fortran as the primary coding medium and the hardware biased toward numerically intensive applications. © 1988 IEEE

Date

01 Jan 1988

Publication

IEEE TC

Authors

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