A multi-bit error detection scheme for DRAM using partial sums with parallel counters

Abstract

Multi-bit soft errors are a key reliability concern for advanced technology memories. Along with soft errors, multi-bit retention errors due to leakage are also a concern for DRAM memory. We have developed a fast, multi-bit/all-bit error detection scheme based on the unidirectional error property of DRAM. The scheme allows tradeoff between detection speed, code length and circuit area. Electrical simulation results at 45-nm SOI technology for a 128-bit data-path indicate that the error detection can be achieved in a single clock cycle with clock frequency greater than 3.3 GHz. © 2008 IEEE.