IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

A method for reduced-order modeling and simulation of large interconnect circuits and its application to PEEC models with retardation

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The continuous improvement in the performance and the increases in the sizes of VLSI systems make electrical interconnect and package (EIP) design and modeling increasingly more important. Special software tools must be used for the design of high-performance VLSI systems. Furthermore, larger and faster systems require larger and more accurate circuit models. The partial element equivalent circuit (PEEC) technique is used for modeling such systems with three-dimensional full wave models. In this paper, we present a practical, readily parallelizable procedure for generating reduced-order frequency-domain models from general full wave PEEC systems. We use multiple expansion points, and piecemeal construction of pole-residue approximations to transfer functions of the PEEC systems, as was used in the complex frequency hopping algorithms. We consider general, multiple-input/multiple-output PEEC systems. Our block procedure consists of an outer loop of local approximations to the PEEC system, coupled with an inner loop where an iterative model-reduction method is applied to the local approximations. We systematically divide the complex frequency region of interest into small regions and construct local approximations to the PEEC system in each subregion. The local approximations are constructed so that the matrix factorizations associated with each of them are the size of the original system and independent of the order of the approximation. Results of computations on these local systems are combined to obtain a reduced-order model for the original PEEC system. We demonstrate the usefulness of our approach with three interesting examples. © 2000 IEEE.