J. Paul Roth
IEEE TC
This paper describes an algorithm for the computation of tests to detect failures in asynchronous sequential logic circuits. It is based upon an extension of the D-algorithm [1]. Discussion of experience with a program of the procedure is given. © 1971, IEEE. All rights reserved.
J. Paul Roth
IEEE TC
Willard G. Bouricius, Edward P. Hsieh, et al.
IEEE TC
David E. Muller, Gianfranco R. Putzolu
Journal of Computer and System Sciences
Willard G. Bouricius, Edward P. Hsieh, et al.
IEEE TC