A gradient descent bias optimizer for oscillator phase noise reduction demonstrated in 45nm and 32nm SOI CMOS
This paper presents a technique for minimizing the phase noise of a CMOS PLL's oscillator. An integrated state-machine implements a gradient descent optimization algorithm to find the VCO bias voltage with the minimum frequency sensitivity to the bias voltage. This suppresses noise up-conversion within the oscillator for a key class of noise sources. The scheme is demonstrated in two separate PLLs. In a 45nm SOI CMOS 13.5-to-16.5 GHz PLL the phase noise is reduced from -90 to -103 dBc/Hz at 1MHz offset measured from a 15.5GHz carrier. In a 32nm SOI CMOS 17.5GHz-to-21 GHz, the phase noise is reduced from -78.8 to -84.2 at 100kHz offset from an 18.1GHz carrier.