A general approach for the performance assessment of nanoscale silicon FETs

Abstract

Various nonplanar, multigate field-effect transistors (FET) structures have been reported that offer better gate control than planar MOSFETs. In the nanometer regime, however, multigate (nanowire) structures also suffer strong quantum confinement, which causes deleterious effects such as large threshold voltage variation. In this paper, we propose a general approach to compare planar versus nonplanar FETs with the consideration of both electrostatic integrity (gate control) and quantum confinement (the so-called "EQ approach"). With this EQ approach, we show that the cylindrical wire FET and the planar double-gate MOSFET have approximately equal scaling capability for a (001)-oriented wafer, while the nonplanar wire structures are significantly better for other wafer orientations [e.g., (011)] where the effective mass in the confinement direction of the planar MOSFET is relatively small. © 2004 IEEE.