Richard R. Grzybowski, B. Roe Hemenway, et al.
PS 2007
A four-terabit packet switch supporting long round-trip times is described. The switch uses a combined input- and crosspoint-queued structure with virtual output queuing at the ingress. The system is build from four different CMOS ASIC building blocks, using a total of 40 chips for the switching core and 64 fabric interface chips on the line cards. Benefits include high scalability, thoroughput and quality of service.
Richard R. Grzybowski, B. Roe Hemenway, et al.
PS 2007
Cyriel Minkenberg, François Abel, et al.
IEEE Micro
Robert Birke, Lydia Y. Chen, et al.
IWQoS 2013
Cyriel Minkenberg, Ronald P. Luijten, et al.
Computer Communication Review