Ana Jokanovic, Jose Carlos Sancho, et al.
IPDPS 2015
A four-terabit packet switch supporting long round-trip times is described. The switch uses a combined input- and crosspoint-queued structure with virtual output queuing at the ingress. The system is build from four different CMOS ASIC building blocks, using a total of 40 chips for the switching core and 64 fabric interface chips on the line cards. Benefits include high scalability, thoroughput and quality of service.
Ana Jokanovic, Jose Carlos Sancho, et al.
IPDPS 2015
Ronald Luijten, Cyriel Minkenberg, et al.
ACM/IEEE SC 2005
Robert Birke, Daniel Crisan, et al.
HPSR 2012
Ana Jokanovic, Cyriel Minkenberg, et al.
INA-OCMC 2012