A comprehensive simulation study of strained-Si/SiGe nMODFET scaling for RF applications

Abstract

2-dimensional (2-D) device simulations have been performed to study the scaling of strained-Si/SiGe nMODFETs. Device fabrication has been conducted to verify the simulation results. It is found that lateral scaling alone cannot improve the device performance. In order to achieve high speed (fT > 300 GHz), acceptable voltage gain (GV > 10) and good turnoff characteristics (Ion/Ioff > 103) for RF applications, vertical scaling of the layer structure and source/drain junctions is also required. Preliminary experimental results support the scaling theory.