Jose Bonan, Christoph Hagleitner, et al.
ESSCIRC 2006
A fast 128-bit end-around carry adder is designed and fabricated as part of the POWER6 floating-point unit in a 65nm SOI process technology. Efficient use of static circuits and careful balance of the look-ahead tree enable our floating-point design to operate beyond 5GHz with 1.1V supply. © 2006 IEEE.
Jose Bonan, Christoph Hagleitner, et al.
ESSCIRC 2006
Sae Kyu Lee, Ankur Agrawal, et al.
IEEE JSSC
James Warnock, Y.-H. Chan, et al.
ISSCC 2011
Charles F. Webb, Carl J. Anderson, et al.
IEEE Journal of Solid-State Circuits