Yiu-Hing Chan, Prabhakar Kudva, et al.
DAC 2003
A power and area efficient 108-bit end-around carry adder is implemented using IBM 65nm SOI technology. The adder is used for a multiply-add fused (MAF) floating point unit. Careful balance of the adder structure and structure-aware layout techniques enabled this adder to have a latency of 270ps at power consumption of 20mW with 1V supply. © 2008 Springer Science+Business Media, LLC.
Yiu-Hing Chan, Prabhakar Kudva, et al.
DAC 2003
Brian Curran, Eric Fluhr, et al.
IBM J. Res. Dev
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ISSCC 2013
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ESSCIRC 2006