A 20 ns 64K (4K X16) NMOS RAM

Abstract

This paper describes a 64K (4Kx 16) NMOS RAM which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 μm, and an effective channel length of 1.2μm. The chip is organized physically into four 16K blocks. Cell area is 292 μm2 with a chip area of 32.6 mm2. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described. © 1984 IEEE.