A 10-ns Hybrid Number System Data Execution Unit for Digital Signal Processing Systems

A high-performance data execution unit suitable for computation-intensive digital signal processing systems is described. This unit uses the hybrid number system approach to speed up the basic arithmetic operations while remaining compatible with a standard IEEE 32-b floating-point format. However, all the arithmetic operations are performed in the 32-b logarithmic number system (LNS) domain. This chip is designed using a 3.4-V 0.8-μm CMOS technology with double-layer metalization. Conversion algorithms, chip architecture, design methodology, and major circuit components are discussed. A macrocell design methodology is adopted in order to achieve the highperformance custom design circuits with the convenience of an automatic layout system. Computer simulations indicate that all the 32-b floating-point arithmetic operations (multiplication, division, squaring, and square root) can be executed in 10 ns. Extension of this unit into a 64-b double-precision floating-point system and multiply-accumulation applications are also presented. © 1991 IEEE