In summary, a novel technique for a configurable multiple boost plane SRAM operation is presented, achieving ultra-low Vmin for memories targeting use in cryogenic circuits for quantum computing. Full functionality for 6T compile-able SRAM is shown from RT down to 6K (VCSmin~ 0.31 V), leveraging boost techniques. Reduced voltage promises benefit for scaled cryogenic qubit control (Fig. 2). Our results show a 100X reduction in leakage power at 6K compared to RT for evaluated SRAM design. The use of smaller SRAM banks enables better control of Vmin, resulting in low power and high yield.
Future work hinges on optimization of the power of boost mode and demonstration of this technique in ultra-low-voltage cryogenic digital processor used in a fully integrated QSC.