VLSI 2022
Conference paper

A 0.31V Vmin Cryogenic SRAM Based Memory in 14nm FinFET Technology For Quantum Application


A fully functional compile-able 4.1Kb 6T SRAM macro in 14nm FinFET technology targeting low-voltage cryogenic operation with a configurable multi-supply boosting capability with VCSmin of 0.23V (room temperature) and 0.31V (6K) is demonstrated.

Authors’ notes

Cryogenic quantum state controllers (QSC) can be realized as mixed-signal arbitrary waveform generators, incorporating custom analog and custom digital processor designs. SRAM is a critical element in such custom digital processor designs. Key considerations for the digital design include:

  1. Achieving target performance,
  2. Sufficient storage for waveform and other data, and
  3. Reduction in total power of the processor.

The analog section of the generator consists of a digital to analog converter (DAC), base band filter (BBF), mixer, attenuator, transformer and other logic to generate RF control pulses needed for qubits. Instruction memory holds programs for waveform generation and sequencing needed for DAC. Data memory serves as a general-purpose scratchpad. Waveform memory stores modulated RF waveforms. Memory access power is a significant proportion of overall digital power. Memory access power is a significant proportion of overall digital power. Thus, ultra-low-voltage, low-power, robust cryo-memory implementations are highly desirable for future scaled cryo CMOS-based quantum computing systems.

A six-transistor SRAM is the workhorse of the industry. However, its lowest operating voltage (Vmin) is limited even at room temperature (RT) due to the compromises imposed by its use of a shared read/write port. Overcoming this limitation is key to achieving Vmin reduction. Due to the limited cooling power of dilution fridge technology, circuit power needs to be minimized. However, at cryogenic temperatures, FET threshold voltages rise by as much as 100mV-150mV, demanding higher operating voltages — hence higher power to maintain performance margins. Reducing Vmin can reduce SRAM power; further, if the system’s minimum digital voltage is set by the SRAM, achieving low Vmin is a critical path to achieve overall power reduction.

Our approach

Our approach is to use novel circuitry and a small memory bank, along with multiple power domains which would minimize the threshold voltage rise at very low temperatures (e.g. 6K). Thereby low Vmin can be maintained. The technique hinges on boosting two power supplies: one to memory arrays and the wordline driver, and the other one for peripheral logic. Two transistors (Fig. 1: PFET and NFET) are connected in parallel with one common node to a power supply, and the other common node acts as a virtual node, which supplies power to SRAM.

This virtual node is also connected to an interconnect capacitor whose strength can be varied in increments. When input to PFET goes from low to high, NFET acts as a capacitor as its source; drain and gate are connected to supply voltage. As a result, the virtual node dynamically increases initially and returns to its original value when the leakages dominate. This increase minimizes the increase in threshold voltage observed at low temperatures. Also separating two supply planes and use of a smaller bank of memory improves efficiency and yield with respect to mismatches.

Fig 1. Boost generator with device and interconnect capacitances.
Fig 1. Boost generator with device and interconnect capacitances.


In summary, a novel technique for a configurable multiple boost plane SRAM operation is presented, achieving ultra-low Vmin for memories targeting use in cryogenic circuits for quantum computing. Full functionality for 6T compile-able SRAM is shown from RT down to 6K (VCSmin~ 0.31 V), leveraging boost techniques. Reduced voltage promises benefit for scaled cryogenic qubit control (Fig. 2). Our results show a 100X reduction in leakage power at 6K compared to RT for evaluated SRAM design. The use of smaller SRAM banks enables better control of Vmin, resulting in low power and high yield.

Fig 2. By adjusting boost clock timing lower Vmin can be achieved at 6K.
Fig 2. By adjusting boost clock timing lower Vmin can be achieved at 6K.

Future work

Future work hinges on optimization of the power of boost mode and demonstration of this technique in ultra-low-voltage cryogenic digital processor used in a fully integrated QSC.


12 Jun 2022


VLSI 2022