60 GHz transmitter circuits in 65nm CMOS

Abstract

This work presents fundamental building blocks for a 60GHz transmitter front-end. The circuits are implemented in a 65nm bulk CMOS technology, operate from a 1.2V supply, and attain state-of-the-art performance for multi-Gb/s wireless applications. A single-stage, single-ended, power amplifier achieves peak power gain of 4.5dB, output 1dB compression point of 6dBm, saturated power of 9dBm, and peak power added efficiency of 8.5% at 62GHz. A double-balanced, Gilbert-based, up-conversion mixer achieves 6.5dB of conversion loss and output 1dB compression point of -5.0dBm with LO of 50GHz and IF of 10GHz. Millimeter-wave design considerations and measurements over frequency and temperature are discussed. © 2008 IEEE.