Basanth Jagannathan, Mounir Meghelli, et al.
IEEE Electron Device Letters
We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high fMAX (338 GHz) and a low fT (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) fT and fMAX, a simple figure of merit proportional to √fT/RBCCB with RB and CCB extracted from S-parameter measurement is best correlated to the minimum gate delay.
Basanth Jagannathan, Mounir Meghelli, et al.
IEEE Electron Device Letters
N. Feilchenfeld, Frederick A. Anderson, et al.
IEDM 2015
Ilter Ozkaya, Alessandro Cevrero, et al.
IEEE JSSC
Behnam Analui, Alexander Rylyakov, et al.
IEEE Journal of Solid-State Circuits