Abstract
As CMOS scaling is approaching 0.1 μm channel length, this paper examines a number of key device and technology issues which will ultimately determine the limit of room temperature scaling. High speed and high transconductance (750 mS/mm for n, 400 mS/mm for p) sub-0.1 μm nMOSFET and pMOSFET devices have recently been demonstrated. P+ polysilicon gate was used on 35 Å gate oxide without boron penetration. Very low series resistances (Rrd = 250 Ω-μm for nMOSFET and 500 Ω-μm for pMOSFET) are achieved with 500-700 Å-deep n+ and p+ source-drain extensions. These results indicate that it is possible to scale CMOS devices to 0.1 μm channel length. Beyond 0.1 μm, however, conventional CMOS performance at room temperature levels off subject to off-current and threshold voltage requirements. A number of possibilities for further performance enhancement, such as SOI, SiGe channel, double-gate device, and low temperature CMOS are discussed.