- GB
- 2626690
Carl Radens
Overview
Title
Semiconductor Memory Research and Development
Location
IBM Research - Albany
Albany, NY USA
Bio
Memory Research for Hybrid Cloud, Systems and AI
Focused on the R&D of cache memory used in computer chips, high-performance processors, AI, hybrid cloud, mobile communication, system-on-chip (SoC), entertainment processors, graphics processors, and ASICs, for foundry, platform and custom applications.
https://www.linkedin.com/in/carlradens/
h-index = 46 overall, >9679 citations
https://scholar.google.com/citations?hl=en&user=6bLa6jIAAAAJ
> 390 issued US patents
IEEE Author Profile (subset of publications)
https://ieeexplore.ieee.org/author/37331431800
Selected Publications (also see LinkedIn profile):
- High-Performance Nanosheet Technology Optimized for 77 K, IEDM 2023
- Performance of stacked nanosheet gate all around FET’s with EUV patterned gate and sheets, 2021
- A comparative analysis of EUV sheet and gate patterning for beyond 7nm gate all around stacked nanosheet FET’s, 2020
- Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM, 2019
- A 7nm CMOS Technology Platform for Mobile and High Performance Compute Application, 2017
- A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM, 2016
- 'Super-Fast Physics-based Methodology for Accurate Memory Yield Prediction', 2015
- High Performance 14nm SOI FinFET CMOS Technology with 0.0174um2 embedded DRAM and 15 Levels of Cu Metallization, 2014
- Fully-depleted planar technologies and static RAM
- A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements
- Embedded memory considerations in SOI
- A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate
- A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing
- Are Design Tools and Methodologies Measuring up to the Challenges of the DFM Era?
- Characterization of across-device linewidth variation (ADLV) for 65-nm logic SRAM using CDSEM and linewidth roughness algorithms
- Fluctuation limits & scaling opportunities for CMOS SRAM cells
- High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- Technologies for scaling vertical transistor DRAM cells to 70 nm
- Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
- Leakage current and reliability evaluation of ultra-thin reoxidized nitride and comparison with silicon dioxides
- A highly cost efficient 8F/sup 2/ DRAM cell with a double gate vertical transistor device for 100 nm and beyond
- A lithographically-friendly 6F2 DRAM cell
- + more
Honors & Awards
- Outstanding Research Accomplishment: Technology Development, Qualificaiton, and Design Technology Co-Optimization for 7nm Server Processors, 2021
- Invention Achievement Award 100th Plateau, 2020
- Excellence and Eminence Award, 2019
- Lifetime Master Inventor
- Outstanding Technical Achievement Award in Appreciation for 45 nm Bulk Technology Development
- Outstanding Technical Achievement Award in Appreciation for P6 Worlds Fastest Processor
- Corporate Technical Recognition Event (CTRE) 3X
- Division Portfolio Awards for High-Value Patents (17X)