2015 | 2014 | 2013 | 2012 | 2011 | 2009 | 2008 | 2007 | 2006 | 2005 | 2004 | 2003 | 2002
- L. Kull
“Low-Power CMOS ADCs for 100+Gb/s Wireline Communications”
IEEE International Solid-State Circuits Conference (ISSCC), Wireline Forum (invited) 2015. - P. A. Francese, T. Toifl, M. Braendli, C. Menolfi, M. Kossel, T. Morf
“Continuous-Time Linear Equalization with Programmable Active-Peaking Transistor Arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap Speculative DFE Receiver”
accepted at IEEE International Solid-State Circuits Conference (ISSCC), 2015. - T. M. Andersen, F. Krismer, J. W. Kolar, T. Toifl, C. Menolfi, L. Kull
“A Feedforward Controlled On-Chip Switched-Capacitor Voltage Regulator Delivering 10W in 32nm SOI CMOS”
accepted at IEEE International Solid-State Circuits Conference (ISSCC), 2015.
- T. M. Andersen, F. Krismer, J.W. Kolar, T. Toifl, C. Menolfi, L. Kull, T. Morf, M. Kossel, M. Brandli, P. Buchmann, P. A. Francese
”A deep trench capacitor based 2:1 and 3:2 reconfigurable on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS”
29th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2014. - T. M. Andersen, F. Krismer, J.W. Kolar, T. Toifl, C. Menolfi, L. Kull, T. Morf, M. Kossel, M. Brandli, P. Buchmann, P. A. Francese
”A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS”
IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014. - L. Kull, T. Toifl, M. Schmatz, P.A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T.M. Andersen, Y. Leblebici
“A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS”
IEEE International Solid-State Circuits Conference (ISSCC), 2014. - T. Toifl
“Low-Power Equalization and CDR for 10-28Gb/s SerDes”
Wireline Forum of the IEEE International Solid-State Circuits Conference (ISSCC), 2014 (invited). - L. Kull, J. Pliva, T. Toifl, M. Schmatz, P.A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T.M. Andersen, Y. Leblebici
“A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS”
IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014. - M. Kossel, C. Menolfi, T. Toifl, P.A. Francese, M. Brandli, T. Morf, L. Kull, T.M. Andersen, H. Yueksel
“A DDR3/4 memory link TX supporting 24–40 Ω, 0.8–1.6 V, 0.8–5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI”
40th European Solid State Circuits Conference (ESSCIRC), 2014. - P.A Francese, T. Toifl, M. Brandli, P. Buchmann, T. Morf, M. Kossel, C. Menolfi, L. Kull, T.M. Andersen, H. Yueksel
“A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS”
40th European Solid State Circuits Conference (ESSCIRC), 2014. - T. Toifl, P. Buchmann, T. Beukema, M. Beakes, M. Brandli, P.A Francese, C. Menolfi, M. Kossel, L. Kull, T. Morf
“A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os”
40th European Solid State Circuits Conference (ESSCIRC), 2014.
- L. Kull, T. Toifl, M. Schmatz, P. A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T. Meyer Andersen, Y. Leblebici
“A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS”
IEEE Int'l Solid-States Circuits Conf. “ISSCC 2013”, San Francisco, USA. - L. Kull, T. Toifl, M. Schmatz1, P. A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T. Meyer Andersen, Y. Leblebici
“A 35mW8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS”
VLSI Circuits Symposium 2013, Kyoto, Japan. - M. Kossel, C. Menolfi, T. Toifl, P. A. Francese, M. Brändli, P. Buchmann, L. Kull, T. Meyer Andersen, T. Morf
“A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s Thin-Oxide DDR Transmitter with 1.9-to-7.6V/ns Clock- Feathering Slew-Rate Control in 22nm CMOS”
IEEE Int'l Solid-States Circuits Conf. “ISSCC 2013”, San Francisco, USA. - T.M. Andersen, F. Krismer, J.W. Kolar, T. Toifl, C. Menolfi, L. Kull, T. Morf, M. Kossel, M. Brandli, P. Buchmann, P.A. Francese
“A 4.6W/mm2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS”
Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2013. - M. A. Kossel, T. Toifl, P. A. Francese, M. Brändli, C. Menolfi, P. Buchmann, L. Kull, T. Meyer Andersen, T. Morf
“An 8Gb/s 1.5mW/Gb/s 8-Tap 6b NRZ/PAM-4 Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22nm CMOS”
IEEE Journal of Solid-State Circuits 48(12) 2013, pp. 3268-3284. - T. Morf, B. Klein, M. Despont, U. Drechsler, L. Kull, D. Corcos, D. Elad, N. Kaminski, M. Braendli, C. Menolfi, M. Kossel, P.A. Francese, T. Toifl, D. Plettemeier
“Room-temperature THz imaging based on antenna-coupled MOSFET bolometer”
IEEE 26th International Conference on Micro Electro Mechanical Systems (MEMS), 2013.
- T. Toifl, C. Menolfi, M. Ruegg, R. Reutemann, A. Prati, D. Gardellini, M. Brändli, M. Kossel, P. Buchmann, P. A. Francese, T. Morf
“A 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS”
IEEE Journal of Solid-State Circuits 47(4) 2012, pp. 897-910. - C. Menolfi, J. Hertle, T. Toifl, T. Morf, D. Gardellini, M. Braendli, P. Buchmann, M. Kossel
“A 28Gb/s source-series terminated TX in 32nm CMOS SOI”
IEEE Int'l Solid-State Circuits Conf. “ISSCC 2012”, San Francisco, USA. - J. Bulzacchelli, T. Beukema, D, Storaska, P. Hsieh, S. Rylov, D. Furrer, D. Gardellini, A. Prati, C. Menolfi, D. Hanson, J. Hertle, T. Morf, V. Sharma, K. Kelkar, H. Ainspan, W. Kelly, G. Ritter, J. Garlett, R. Callan, T. Toifl, D. Friedman
“A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology”
IEEE Int'l Solid-State Circuits Conf. “ISSCC 2012”, San Francisco, USA. - T. Toifl, M. Ruegg, R. Inti, C. Menolfi, M. Brandli, M. Kossel, P. Buchmann, P.A. Francese, T. Morf
“A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS”
Digest of Technical Papers VLSI Circuits Symposium 2012, Honolulu, USA.
- T. Toifl
“Design Challenges, Latest Achievements and Future Directions of High-Speed I/Os”
IEEE Int'l Solid-States Circuits Conf. (ISSCC) 2011, Wireline Forum, San Francisco, USA, 2011 (invited). - R. Inti, A. Elshazly, B. Young, Wenjing Yin, M. Kossel, T. Toifl, P.K. Hanumolu
“A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS”
IEEE Int'l Solid-States Circuits Conf. (ISSCC) 2011. - C. Menolfi, T. Toifl, M. Rueegg, M. Braendli, P. Buchmann, M. Kossel, T, Morf
“A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI”
IEEE Int'l Solid-States Circuits Conf. (ISSCC) 2011. - T. Toifl, C. Menolfi, M. Ruegg, R. Reutemann, A. Prati, D. Gardellini, M. Brändli, M. Kossel, P. Buchmann, P. A. Francese, T. Morf
“A 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS”
Digest of Technical Papers, VLSI Circuits Symposium 2011, Kyoto, Japan.
- M. Kossel, T. Morf, J. Weiss, P. Buchmann, C. Menolfi, T. Toifl, M. Schmatz
“LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS”
IEEE Journal of Solid-State Circuits 44(2) 2009, pp. 436-449. - T. Toifl, C. Menolfi, P. Buchmann, M. Kossel, T. Morf, M. Schmatz
“A 1.25–5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS”
IEEE Journal of Solid-State Circuits 44(11) 2009, pp. 2901-2910. - M. Kossel, C. Menolfi, M. Braendli, P. Buchmann, T. Morf, T. Toifl, M. Schmatz
“Design of source-series-terminated transmitters with T-coils”
CMOS Emerging Technologies Workshop CMOSET, Sept. 23-25, 2009, Vancouver, Canada. - M. Kossel, T. Morf, P. Buchmann, M. Schmatz, C. Menolfi, T. Toifl
“Switched inductor with wide tuning range and small inductance step sizes”
IEEE Microwave and Wireless Components Letters (MWCL) 19(8), 2009, pp. 515-517 - T. Toifl, C. Menolfi, M. Kossel, M. Braendli, T. Morf, P. Buchmann, M. Schmatz
“Low Power and Compact Transceivers for High-Speed Wireline Communications”
CMOS Emerging Technologies Workshop (CMOSET), Feb. 18-20, 2009, Banff, Canada. - R. Reutemann, M. Ruegg, F. Keyser, J. Bergkvist, D. Dreps, T. Toifl, M. Schmatz
“A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS”
IEEE Journal of Solid-State Circuits 45(12) 2010, pp. 2850-2860.
- T. Toifl
“Design Techniques for Ultra-Low Power and Compact Transceivers in CMOS”
Wireline Forum of the International Solid-State Circuits Conference (ISSCC) 2008, Feb. 2008 (invited). - M. Kossel, C. Menolfi, J. Weiss, P. Buchmann, G. von Bueren, L. Rodoni, T. Morf, T. Toifl, M. Schmatz
“A T-coil Enhanced 8.5Gb/s High-swing Source-series-terminated Transmitter in 65nm Bulk CMOS”
International Solid-State Circuits Conf. (ISSCC) 2008," San Francisco. - G. von Bueren, L. Rodoni, A. Huber, R. Brun, D. Holzer, M. Schmatz, H. Jäckel
“6 to 40 Gb/s Quarter-rate CDR with Data-rate Selection in 90 nm Bulk CMOS”
European Solid-State Circuits Conference (ESSCIRC) 2008, Oct. 2008. - M. Kossel, C. Menolfi, J. Weiss, P. Buchmann, G. von Bueren, L. Rodoni, T. Morf, T. Toifl, M. Schmatz
“A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With <-16 dB Return Loss Over 10 GHz Bandwidth”
IEEE Journal of Solid-State Circuits 43(12) 2008, pp. 2905-2920 - T. Toifl, C. Menolfi, P. Buchmann, M. Kossel, T. Morf, M. Schmatz
“A small-area voltage regulator with high-bandwidth supply-rejection using a regulated replica in 45nm CMOS SOI”
IEEE Asian Solid-State Circuits Conference, Fukuoka, Japan, Nov 2008. - C. Berger, L. Dellmann, P. Dill, F. Horst, B. Offrein, M. Schmatz, S. Oggioni, M. Spreafico, G. Macario
“Integration of Optical I/O with Organic Chip Packages”
in Photonics Packaging, Integration, and Interconnects VIII, edited by A.L. Glebov, R.T. Chen, Proc. SPIE, Vol. 6899, 689912 (2008). Proceedings Photonics West 2008, San Jose, CA, January 2008.
- C. Menolfi, T. Toifl, P. Buchmann, C. Hagleitner, M. Kossel, T. Morf, M. Schmatz
“A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI”
International Solid-State Circuits Conference (ISSCC) 2007, Feb. 2007. - T. Toifl, C. Menolfi, P. Buchmann, C. Hagleitner, M. Kossel, T. Morf, M. Schmatz
“A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS”
International Solid-State Circuits Conference (ISSCC) 2007, Feb. 2007. - T. Morf, M. Kossel, J. Weiss, C. Menolfi, T. Toifl, G. von Bueren, P. Buchmann, M. Schmatz
“Wide Tuning Range LC-Oscillator in 65 nm SOI CMOS, Based on Switchable Secondary Inductor”
IET (IEE) Electron. Lett. 43(24) (2007) 1364-1365.
- J. Weiss, M. Kossel, C. Menolfi, T. Morf, M. Schmatz, T. Toifl, H. Jäckel
“A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement”
International Solid-State Circuits Conference (ISSCC) 2006, Digest of Technical Papers, Feb. 2006. - T. Toifl, C. Menolfi, M. Ruegg, R. Reutemann, P. Buchmann, M. Kossel, T. Morf, J. Weiss, M. Schmatz
“A 22-Gb/s PAM-4 receiver in 90-nm CMOS SOI technology”
IEEE Journal of Solid-State Circuits 41(4) 2006, pp. 954-965 - T. Lamprecht, F. Horst, R. Dangel, R. Beyeler, N. Meier, L. Dellmann, M. Gmür, C. Berger, and B. Offrein
“Passive Alignment of Optical Elements in a Printed Circuit Board”
56th Electronic Components and Technology Conference (ECTC 2006), San Diego, 2006. - T. Toifl, M. Schmatz, C. Menolfi
“Low-Complexity Adaptive Equalization for High-Speed Chip-to-Chip Communication Paths by Zero-Forcing of Jitter Components”
IEEE Transactions on Communications 54(9) 2006, pp. 1554-1557.
- C. Menolfi, T. Toifl, M. Ruegg, R. Reutemann, P. Buchmann, M. Kossel, T. Morf, J. Weiss, M. Schmatz
“A 25Gb/s PAM4 transmitter in 90nm CMOS SOI”
International Solid-State Circuits Conference (ISSCC) 2005, Digest of Technical Papers, Feb. 2005 - M. Kossel, P. Buchmann, C. Menolfi, T. Morf, M. Schmatz, T. Toifl, J. Weiss
“Low-jitter 10 GHz multiphase PLL in 90 nm CMOS”
International Solid-State Circuits Conference (ISSCC) 2005, Digest of Technical Papers, Feb. 2005 - T. Morf, C. Menolfi, T. Toifl, C. Kromer, G. Sialm, M. Kossel, J. Weiss
“Electrical and Optical Transceivers for Short-Range Data Communication, Fabricated in VLSI 90 nm Bulk and SOI CMOS Technology”
Proc. IEEE Compound Semiconductor IC Symposium CSICS, Palm Springs, CA, USA, Oct. 30-Nov. 2. 2005 - C. Kromer, G. Sialm, C. Berger, T. Morf, M. Schmatz, F. Ellinger, D. Erni, G. Bona, H. Jäckel
“A 100-mW 4x10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects”
IEEE Journal of Solid-State Circuits 40(12) 2005, pp. 2667-2679. - T. Toifl, C. Menolfi, M. Ruegg, R. Reutemann, P. Buchmann, M. Kossel, T. Morf, J. Weiss, M. Schmatz
“A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links”
IEEE Journal of Solid-State Circuits 40(12) 2005, pp. 2700-2712. - L. Dellmann, T. Lamprecht, S. Oggioni, M. Witzig, R. Dangel, R. Beyeler, C. Berger, F. Horst, and B. Offrein
“Butt-Coupled Optoelectronic Modules for High-Speed Optical Interconnects”
Proc. CLEO/Europe-EQEC 2005, Munich, 2005. - B. Offrein, C. Berger, R. Beyeler, R. Dangel, L. Dellmann, F. Horst, T. Lamprecht, N. Meier, R. Budd, F. Libsch, and J. Kash
“Parallel optical interconnects in printed circuit boards”
Proc. SPIE, vol. 5990, pp. 117-125, 2005. - T. Morf, C. Menolfi, T. Toifl, C. Kromer, G. Sialm, M. Kossel, J. Weiss, P. Buchmann, C. Berger, and M. Schmatz
“Electrical and optical transceivers for short-range data communication, fabricated in VLSI 90-nm bulk and SOI CMOS technology”
Compound Semiconductor Integrated Circuit Symposium, 2005. CSICS '05. IEEE, 2005.
- C. Kromer, G. Sialm, T. Morf, M. Schmatz, F. Ellinger, D. Erni, H. Jäckel
“A low-power 20-GHz 52-dB transimpedance amplifier in 80-nm CMOS”
IEEE Journal of Solid-State Circuits 39(6) 2004, pp. 885-894. - M. Kossel, T. Morf, W. Baumberger, A. Biber, C. Menolfi, T. Toifl, M. Schmatz
“A multiphase PLL for 10 Gb/s links in SOI CMOS technology”
Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers, June 2004. - G.-L. Bona, B. Offrein, U. Bapst, C. Berger, R. Beyeler, R. Budd, R. Dangel, L. Dellmann, and F. Horst
“Characterization of parallel optical-interconnect waveguides integrated on a printed circuit board”
Proc. SPIE, vol. 5453, 2004. - C. Berger, U. Bapst, G.-L. Bona, R. Dangel, L. Dellmann, P. Dill, M. A. Kossel, T. Morf, B. Offrein, and M. L. Schmatz
“Design and implementation of an optical interconnect demonstrator with board-integrated waveguides and microlens coupling”
Biophotonics/Optical Interconnects and VLSI Photonics/WBM Microcavities, 2004 Digest of the LEOS Summer Topical Meetings, 2004. - R. Dangel, U. Bapst, C. Berger, R. Beyeler, L. Dellmann, F. Horst, B. Offrein, and G.-L. Bona
“Development of a low-cost low-loss polymer waveguide technology for parallel optical interconnect applications”
Biophotonics/Optical Interconnects and VLSI Photonics/WBM Microcavities, 2004 Digest of the LEOS Summer Topical Meetings, 2004.
- C. Berger, M. Kossel, C. Menolfi, T. Morf, T. Toifl, and M. Schmatz
“High-density optical interconnects within large-scale systems”
Proc. SPIE, vol. 4942, pp. 222-235, 2003. - T. Toifl, C. Menolfi, M. Kossel, T. Morf, M. Schmatz
“A 23GHz differential amplifier with monolithically integrated T-coils in 0.09µm CMOS technology”
IEEE Microwave Symposium Technical Digest, Philadelphia, June 2003.