The continued shrinking of CMOS feature sizes allows us to build high-speed interconnect circuits at ever higher data rates.
We explore new circuit architectures for transmitter and receiver circuits together with next-generation CMOS technology. The goal is to achieve the highest possible data rate at the lowest power consumption and smallest chip area.
Typical circuits include
- Transmitter/drivers circuits [2012-2, 2011-3, 2008-4, 2008-2, 2007-1, 2005-1, 2005-3, 2005-4] with integrated feed-forward equalization (FFE)
- DDR TX [2014-6, 2013-3].
- Optical I/Os [2008-6, 2006-3, 2005-3, 2005-4, 2005-7, 2004-1, 2004-3, 2004-4, 2004-5].
- High-bandwidth input amplifiers/equalizer circuits [2015-2, 2014-7, 2014-4, 2013-1, 2012-3, 2012-4, 2011-1, 2011-4, 2006-1, 2006-2, 2006-4, 2004-1, 2003-2].
- Receiver circuits with clock and data recovery (CDR) capability
[2014-4, 2014-7, 2011-4, 2009-6, 2008-3, 2007-2, 2005-5]. - Phase-locked loops (PLLs) for clock generation [2009-1, 2009-4, 2007-3, 2005-2, 2005-5, 2004-2].
- Voltage regulators and circuits to cope with device variability [2009-2, 2008-7].
- Power converters [2015-3, 2014-1, 2014-2, 2013-4].
- Digital I/O architectures [2014-5, 2014-8, 2013-5].
- High-speed data converters [2015-1, 2014-3, 2014-5, 2013-1, 2013-2].
- THz image detector [2013-6].
