Tutorials - Monday, 17 Nov 2014

The HVC 2014 tutorials offer an opportunity to extend knowledge and gain exposure to research challenges and state-of-art practice in various fields of verification.

The tutorials day of HVC 2014 will be held on November 17. Like the main conference, the tutorials day will also take place at IBM Research – Haifa, located on the University of Haifa campus, Mount Carmel in Haifa, Israel.

Verification - From Fundamental Technologies to Advanced Research.

Table header results




Opening Remarks,
Raviv Gal, IBM Research – Haifa


Pre-to-Post Validation Continuum - Functional Coverage and More,
Yael Abarbanel, Intel

Abstract: The move towards the SoC paradigm comes with a compelling requirement for shorter time-to-market (TTM). Traditional validation solutions are no-longer adequate to achieve the aggressive roadmap targets. To address the requirements for diminishing TTM, the validation world needs to shift to a holistic validation approach, considering the entirety of the product development process, and promoting the synergy between pre-silicon and post-silicon validation.

The validation spectrum is the matrix of platforms (simulation, FPGA, Emulation, Virtual Prototyping, silicon), and validation activities (test execution, debug, coverage). We need a global optimization of all validation activities by performing each activity only once, at the right time and on the appropriate validation platform.

Today, functional coverage is a standard quality indicator for the design correctness and validation process. It is used to improve the quality of regressions, to optimize test suites, and to indicate the validation maturity. Coverage-based validation is a well-established functional validation methodology both in pre-si platforms and post-si. Precious project resources are invested in the definition of coverage spaces, their validation, and analysis of coverage results. However, this effort is duplicated across the various validation platforms in pre-si and post-si. Reuse is minimal due to the inherent differences between the various validation platforms (traceability, observability). In this discussion we articulate the challenges in coverage sharing across the validation continuum and discuss solution directions.




Sparse Statespaces and Their Challenges to Verification,
Johannes Kösters, IBM

Abstract: High end processor chips are very similar to SoC Designs in many regards. They are comprised of multiple cores interacting with each other and with IO and memory structures. In order to manage such designs and to implement essential reliability, availability and serviceability features to those chips they come with a built in service architecture implementing features like Power On, Built-In Self-Test, register access methods and other functions used for debug and problem analysis.

This implementation is though not a general purpose design, but is more defined by the superset of its use cases. The design is hierarchical and is mostly based on register operations triggering certain functions. This is a sparse state space, where functions are dependent on selected, defined sequences of register operations. In this tutorial, we present the challenges and discuss a few solution directions that are being pursued in this space at IBM.




Creating Portable Tests with a Graph-Based Test Specification,
Avidan Efody, Mentor Graphics

Abstract: There is a growing emphasis on SoC- and system-level testing as the number of processor cores in designs increases. Verification using high-level verification languages (HVLs), such as SystemVerilog, in simulation is still critical at the block level. However, verification must now extend to drive embedded software running on the processor cores, and run in simulation, emulation, FPGA prototypes, and even first silicon.

System level verification engineers do not enjoy the benefits of a standardized testbench language such as SystemVerilog, nor a standard class library methodology such as UVM. Unlike their IP block level verification engineering counterparts, system level verification engineers are left to a variety of languages and methodologies.

This tutorial will provide an overview of a graph-based test description language that raises the level of verification abstraction to address system level challenges. A graph-based test specification provides an effective test description and efficient test execution to address system level verification challenges. It raises the level of abstraction in describing both system level stimulus and verification goals (metrics), while not restricting system level verification teams to a pre-determined language or methodology.

Among other benefits, using a graph-based approach enables the highest degree of verification re-use, from IP block to sub-system to full-system level verification. A graph-based description supports verification in SystemVerilog, VHDL, C, C/C++, assembly, and even other non-traditional base languages. And it also can be extended from simulation to emulation to FPGA prototyping, and even silicon validation.

This tutorial will provide an introduction to the graph-based stimulus and metrics description, and will show how it enables the efficient creation of portable and effective tests.




Achieving Sign-off with End-to-End Formal,
Vigyan Singhal, Oski Technology

Abstract: This tutorial focuses on the most complex yet most rewarding usage of formal - using End-to-End formal to replace simulation and achieve Sign-off. The four Cs of the Formal Sign-off methodology, checkers, constrains, complex and coverage, will be presented. We will discuss the complexity barriers to achieving proof convergence with formal tools, and describe some techniques to overcome these barriers within a given project schedule.


End of Tutorial Day

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Keynote Speakers

  • Prof. Moshe Vardi, Rice University
  • Wolfgang Roesner, Fellow, IBM
  • Prof. Martin Vechev, ETH Zürich
  • Harry Foster, Chief Verification Scientist, Mentor Graphics
  • Ziv Binyamini, Corporate VP & CTO, System and Software Solutions, Cadence

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