Optimization objectives and models of variation for statistical gate sizing
- Matthew R. Guthaus
- Natesan Venkateswaran
- et al.
- 2005
- GLSVLSI 2005
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3 results at GLSVLSI 2005
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution
- G.G. Lopez
- G. Fiorenza
- et al.
- 2005
- GLSVLSI 2005
Characterizing the VCO Jitter Due to the digital simultaneous switching noise
- Tian Xia
- Peilin Song
- et al.
- 2005
- GLSVLSI 2005