A 7-nm Four-Core Mixed-Precision AI Chip with 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling
- Sae Kyu Lee
- Ankur Agrawal
- et al.
- 2021
- IEEE JSSC
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60 results for Vijayalakshmi Srinivasan
Integrated analysis of power and performance for pipelined microprocessors
- Victor Zyuban
- David Brooks
- et al.
- 2004
- IEEE TC
A Prefetch Taxonomy
- Viji Srinivasan
- Edward S. Davidson
- et al.
- 2004
- IEEE TC
Active management of data caches by exploiting reuse information
- Edward S. Tam
- Jude A. Rivers
- et al.
- 1999
- IEEE TC
Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators
- Subhankar Pal
- Swagath Venkataramani
- et al.
- 2021
- ISPASS 2021
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference
- Jinwook Oh
- Sae Kyu Lee
- et al.
- 2020
- VLSI Circuits 2020
Memory and Interconnect Optimizations for Peta-Scale Deep Learning Systems
- Swagath Venkataramani
- Vijayalakshmi Srinivasan
- et al.
- 2019
- HiPC 2019
Performance-driven Programming of Multi-TFLOP Deep Learning Accelerators∗
- Swagath Venkataramani
- Jungwook Choi
- et al.
- 2019
- IISWC 2019
A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel
- Eri Ogawa
- Kazuaki Ishizaki
- et al.
- 2019
- COOL CHIPS 2019
A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Trainina and Inference
- Bruce Fleischer
- Sunil Shukla
- et al.
- 2018
- VLSI Circuits 2018