Combinatorial cell design for CMOS libraries
- Frederik Beeftink
- Prabhakar Kudva
- et al.
- 2000
- Integration, the VLSI Journal
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21 results for Leon Stok
Wavefront technology mapping
- Leon Stok
- Mahesh A. Iyer
- et al.
- 1999
- DATE 1999
Don't cares in synthesis: Theoretical pitfalls and practical solutions
- Daniel Brand
- Reinaldo A. Bergamaschi
- et al.
- 1998
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Retiming revisited and reversed
- Guy Even
- Ilan Y. Spillinger
- et al.
- 1996
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BooleDozer: Logic synthesis for ASICs
- Leon Stok
- D.S. Kung
- et al.
- 1996
- IBM J. Res. Dev
Efficient use of large don't cares in high-level and logic synthesis
- Reinaldo A. Bergamaschi
- D. Brand
- et al.
- 1995
- ICCAD 1995
Be careful with don't cares
- D. Brand
- Reinaldo A. Bergamaschi
- et al.
- 1995
- ICCAD 1995
Improving initialization through reversed ret iming
- Leon Stok
- Ilan Spillinger
- et al.
- 1995
- EDTC 1995
High-level synthesis in an industrial environment
- Reinaldo A. Bergamaschi
- R.A. O'Connor
- et al.
- 1995
- IBM J. Res. Dev
Data path synthesis
- Leon Stok
- 1994
- Integration, the VLSI Journal