Publication
IEEE T-ED
Paper

VLSI Limitations from Drain-Induced Barrier Lowering

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Abstract

Drain-induced barrier lowering (DIBL) determines the ultimate proximity of surface diffusions and qualifies as one of the fundamental electrical limitations for VLSI. The important design parameters relating to DIBL are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results. Under normal operating conditions of an IGFET, DIBL produces surface (rather than bulk) injection at the source. Comparison of a base case with a scaled design reveals that simple linear scaling by itself is insufficient for holding DIBL to a tolerable amount. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1979

Publication

IEEE T-ED

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