About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IEEEI 1995
Conference paper
Verification scheme for pipelined vector architectures
Abstract
As a means for improving performance, advanced vector processors use an extension of pipelining, called vector chaining, whereby the execution of independent instructions is overlapped. The complexity of vector chaining architectures, together with their inherent parallelism and asynchrony, renders their verification extremely difficult. This paper presents an efficient simulation-based scheme for verifying such architectures. The scheme presented here can be applied to other verification problems where the simulation expected results is not deterministic but belongs to set a of computable possibilities.