Threshold voltage instabilities in high-κ gate dielectric stacks

Abstract

Over recent years, there has been increasing research and development efforts to replace SiO2 with high dielectric constant (high-κ) materials such as HfO2, HfSiO, and Al2O3. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-κ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed. © 2005 IEEE.