The clock distribution of the power4 microprocessor

Abstract

The clock distribution of the power4 microprocessor was discussed. In the system, 10-hour maximum jitter measurements showed that the phase locked loop (PLL) produces <5 ps cycle compression from the PLL and 30 ps total compression from the PLL plus clock distribution. Performance and schedule challenges of the global clock for the Power4 microprocessor were met using an silicon on insulator (SOI)-specific PLL and a simple streamlined global clock distribution methodology.