About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
Annual ASIC Conference and Exhibit 1997
Conference paper
TDD: A technology dependent decomposition algorithm for LUT-based FPGAs
Abstract
A major drawback of the previous algorithms that perform decomposition and covering for LUT-based FPGA technology mapping is the lack of a fast, and reasonably accurate evaluation scheme for the decomposition phase. In this paper, we will show how a fast covering algorithm can be used as an evaluation engine for the decomposition phase. We show that decomposition has a significant impact on the quality of the final mapping result. More specifically, we show that starting from the same circuit topology, a blind decomposition leads to mapping results that use an average of 70% to 150% more LUTs compared to the results obtained using a technology driven decomposition algorithm. A technology driven decomposition algorithm is developed based on the proposed idea. Experiments on a number of MCNC benchmark circuits show an average of 12% to 72% improvement on the number of LUTs compared to the previously reported results.