Publication
IEEE TC
Paper

Synergistic Fault-Tolerance for Memory Chips

View publication

Abstract

The combined use of redundant circuits and error-correcting codes can result in a fault-tolerance scheme that is vastly more effective than the fault protection provided by either one of these schemes independently. Mathematical analysis shows that this improvement is caused by eliminating the so-called “birthday problem” which limits the effectiveness of error-correcting codes. This solution has been implemented on an experimental 16-Mb memory chip [1], [2]. The analysis of this implementation, and the resulting fault-tolerance synergism are the subject of this paper. Some early fabrication results are also included. They substantiate the existence of this synergism. © 1992 IEEE

Date

01 Jan 1992

Publication

IEEE TC

Authors

Share