Publication
JVSTB
Paper

Sub-20 nm silicon patterning and metal lift-off using thermal scanning probe lithography

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Abstract

The most direct definition of a patterning process' resolution is the smallest half-pitch feature that is capable of transferring onto the substrate. Here, the authors demonstrate that thermal scanning probe lithography (t-SPL) is capable of fabricating dense line patterns in silicon and metal lift-off features at sub-20 nm feature size. The dense silicon lines were written at a half pitch of 18.3 nm to a depth of 5 nm into a 9 nm polyphthalaldehyde thermal imaging layer by t-SPL. For processing, the authors used a three-layer stack comprising an evaporated SiO2 hardmask, which is just 2-3 nm thick. The hardmask is used to amplify the pattern into a 50 nm thick polymeric transfer layer. The transfer layer subsequently serves as an etch mask for transfer into silicon to a depth of ≈65 nm. The line edge roughness (3σ) was evaluated to be less than 3 nm both in the transfer layer and in silicon. The authors also demonstrate that a similar three-layer stack can be used for metal lift-off of high resolution patterns. A device application is demonstrated by fabricating 50 nm half pitch dense nickel contacts to an InAs nanowire.

Date

01 Mar 2015

Publication

JVSTB

Authors

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