Single exposure contacts are dead. Long live single exposure contacts!

Abstract

The paper describes a process/design co-optimization effort based on an SRAM design to enable a single exposure contact process for the 28nm technology half node. As a start, a change to the wiring concept of the standard SRAM design was implemented. The resulting individual contact layer elements may seem even more resolution critical to the casual observer. But in reality, the flexibility for source-mask optimization had been significantly improved. In a second step, wafer targets and mask dimension options (using various kinds of OPC methods and SRAF strategies) were run through several optimization iterations. This included interlevel considerations due to stringent overlap requirements. Several promising SRAM design as well as mask options were identified and experimentally verified to finally converge to an optimum mask and wafer target layout. Said optimum solution still supports an automated OPC approach using standard EDA tools and off the shelf OPC strategies. In a last step, a 1Mbit electrically testable SRAM was designed and manufactured together with alternative SRAM designs and process options. After explaining the changes to the wiring of the SRAM design, the paper discusses in great detail various mask optimization solutions and their consequences on wafer target and printability. Simulation and experimental results are compared and the concluding optimized solution is explained. Furthermore, some key lithography and etch process elements that became the single exposure process enabler are explained in more detail. Finally, the paper will take a look at electrical results of the 1Mbit electrically testable SRAM as the ultimate proof of concept. © 2011 SPIE.