In this paper, we will present a diagnostic test case of a hard-to-find fail condition causing an unexpected partial power on of a chip fabricated in IBM 65 nm bulk technology. In particular, we will describe the fail condition as well as the combined use of electrical testing, optical methodologies, and detailed circuit analysis that were used to reach a successful root cause identification of the problem. In addition, we will show how high resolution mapping of the Light Emission from Off-State Leakage Current (LEOSLC) from the chip was instrumental in leading the investigative effort to the right root cause. The problem was successfully traced to a p-FET used for IDDQ measurement during manufacturing test that caused an undesirable coupling path. Fortunately this specific configuration was unique to this particular design and was easy to fix with a single mask change. © 2012 IEEE.