Conference paper
Design and implementation of the POWER5™ microprocessor
Joachim Clabes, Joshua Friedrich, et al.
ISSCC 2003
The Power7 is IBM's first eight-core processor, with each core capable of four-way simultaneous-multithreading operation. Its key architectural features include an advanced memory hierarchy with three levels of on-chip cache; embedded-DRAM devices used in the highest level of the cache; and a new memory interface. This balanced multicore design scales from 1 to 32 sockets in commercial and scientific environments. © 2006 IEEE.
Joachim Clabes, Joshua Friedrich, et al.
ISSCC 2003
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HCS 2008
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HPCA 2005
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IBM J. Res. Dev