Power reduction by aggressive synthesis design space exploration

Abstract

An increasing focus on design productivity is shifting microprocessor design to more synthesis-centric design methodologies. Low power design is also rising in importance, even for higher performance server chips. This paper proposes a design methodology capitalizing on the relatively low cost of parallel synthesis job submission for design space exploration. By tailoring the design flow for parallel and iterative design space exploration we attempt to maximize the return on investment (ROI) of design effort. The methodology was applied to the IBM POWER7+™ microprocessor to save power during the second release of the chip. This paper provides an overview of the methodology as well as chip hardware measurements showing power savings. © 2013 IEEE.