The etch rate of n-type Si in diluted HF solutions was investigated as a function of the bias voltage applied to the Si/electrolyte interface in the dark and under illumination. It was observed that the etch rate depends very sensitively on the minority carrier flow through this interface. For an illumination intensity of 5.3×1016 photons/cm2 s (γ=550nm) and the depleted Si/electrolyte interface biased slightly (less than 1 V) in reverse, the etch rate is increased by a factor of more than 1000 as compared to the etch rate under open-circuit condition. This effect can be used to create etch patterns during device processing without prior masking the semiconductors. Using the same effect it should be possible to trim the thickness of Si layers on (semi-) insulating substrates for the fabrication of enhancement-mode FETs. © 1984 Springer-Verlag.