Perimeter effects in small geometry bipolar transistors

Abstract

Advanced bipolar technologies with sub-0.5μim emitters have been reported recently [1,2]. Variations of the current gain and cut-off frequency with emitter sizes were observed (3-5). However, the existing interpretations of experimental data are clouded by the interplay of effects of two different origins: (I) geometrical effects due to increasing contribution from device perimeters; (2) variations of intrinsic vertical doping profiles with emitter size in the process J3,3 J. Effects due to the latter category arc exported to he overcome by improved processing technology. Therefore, this study aims for examining the fundamental limits on device performance imposed by geometrical effects. Results of an extensive three-dimensional (3D) device simulation study will be given and compared with experimental results of a 0.25(itn bipolar technology.