Performance consideration for the scaling of sub-micron on-chip interconnections

Abstract

Effects of long wire RC delay to circuit and system performance are investigated for sub-micron on-chip interconnections corresponding to 0.75 to 0.25 um CMOS technologies. A system performance model based on hypothetic microprocessors, projected from previous generations, is introduced for the performance analysis. From the analysis, It is found that using non-scaled upper wiring levels (wide wires) for long global interconnections is the most effective approach to improve system performance with sub-micron-pitch interconnections. It can provide 70 % performance improvement over the wide wire approach, which increase only wire width for long interconnections. The fat wire approach, however, requires some technology modifications, as well as one more wiring level than conventional approaches.