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Publication
Computer Networks and ISDN Systems
Paper
Performance analysis of single-stage, output buffer packet switches with independent batch arrivals
Abstract
A theoretical framework for the analysis of an M × N, output queueing, space-division, non-blocking, packet switch with general i.i.d. batch arrivals is developed. The switch operates in a slotted time-frame with packets arriving to any of its M input ports and destined to any of its N output ports. Assuming a general traffic switching matrix, the (marginal) distribution of the queue size of packets at each of the output ports is obtained. Under FIFO service discipline, the distribution of the waiting time of packets is also obtained. Under finite buffer capacity, the loss probability of packets due to the unavailability of output buffer space is derived. Finally, the sensitivity of the performance measures of the switch under hot-spot traffic conditions is demonstrated. © 1995.