Publication
Integration, the VLSI Journal
Paper

Partitioning and ordering of CMOS circuits for switch level analysis

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Abstract

This paper defines various component types of CMOS circuits that can be determined efficiently. By a proper decomposition of a circuit into its components switch level simulators or symbolic analysers are sped up substantially. Moreover, with the decomposition strategy proposed here a symbolic analysis of certain CMOS structures containing path transistors becomes possible at all. The key step in the partitioning strategy is to divide the set of transistors of a circuit into pass and driver transistors; these transistors are then grouped together to form pass and driver components. The partitioning can be done by efficient graph algorithms based on depth-first search strategies. In some cases a purely combinatorial output function can be computed, even in the presence of feedback. Feedback cycles and the remaining components which are not part of any feedback cycle can be recognised and grouped in linear time. On these groups a topological ordering can be defined which then can be used to schedule a switch level simulation or a symbolic analysis. © 1991 Elsevier Science Publishers B.V.

Date

01 Jan 1991

Publication

Integration, the VLSI Journal

Authors

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