Optimal buffer allocation for packet switches with input and output queueing

Abstract

The authors investigate optimal buffer allocation strategies for a family of space-division packet switches implementing input and output queueing and having varying degrees of speedup. A general model to describe this family of switch is presented. Based on this model, input and output queue-length distributions are obtained for various speedup factors. From these distributions, packet blocking probability for finite-buffer systems can be estimated. The blocking probability is found to consist of convex functions with respect to the finite input and output buffer sizes. Thus, given fixed buffer budgets, there exist optimal placements of buffers among input and output ports to minimize the blocking probability. Numerical results are provided to illustrate these strategies.