OC-12 ATM switch adapter chipset

Abstract

This paper describes the architecture synthesis and implementation of an OC-12 chipset for ATM switches based on the PRIZMA switch chip. It consists of an ATM receive chip, ATM transmit chip and an ATM switch interface chip, which have been realized in a 0.8-micron CMOS technology and run at 800 Mbit/sec. A cost-effective architecture is described based on speeding up the switch port speed over the link speed and cut-through cell processing. As a result, a large inbound cell buffer memory is avoided. The chipset meets switch adapter requirements for the WAN area rather than for workstation or PC adapters. One chipset supports OC-12 speed at 16 thousand connections with the full VPi/VCi field, VP and VC switching, policing, OAM flows, performance monitoring, policing and outbound traffic shaping. Various counters per connection are available to support bandwidth management and accounting functions. Inbound and outbound control traffic insertion and extraction to a high-performance microprocessor interface are supported. The realized chipset demonstrates that a cut-through architecture at high speed is feasible and yields a cost-effective implementation. Furthermore, adapter performance is not dependent on software as all data functions are fully performed in hardware. Requirements for a follow-on version of the chipset due to evolving standards and further cost reduction are described.